The present invention relates generally to a clocking system and method associated with a phase locked loop, and more specifically, to a clocking scheme for maintaining lock of a phase locked loop within an integrated circuit during a normal operation mode and a test mode in which the clock signal is halted, and during the switching from the normal operation mode to the test mode.
The sophistication of a present-day electronic system is a result of complex functions handled by digital integrated circuits making up the electronic system. Digital integrated circuits comprise the majority of electronic circuits in computers and other digital electronic products. Digital integrated circuits can be configured, for example, as a central processing unit (CPU), a programmable logic array (PLA), an application specific integrated circuit (ASIC), or a digital signal processor (DSP). Both the sophistication and speed of operation of these digital integrated circuits have rapidly increased due to improvements in integrated circuit manufacturing and design technologies resulting in smaller and faster devices.
The performance of a computer or electronic device is increased if the delivery time of the central clocking signal is equal to all integrated circuits and components thereof. Unequal delivery times to different components of the system is defined as skew. Therefore, skew basically is a measure of the quality or lack of quality of delivery time of a central clock to different components of the system. To increase the quality of the system, it is desirous to minimize the skew of the system. One factor contributing to the skew of a system is the location of various integrated circuits within the system. The physical distances from the clock to various destination points of the system will differ. As is known in the art, differing physical lengths of conductors equates into differing delay times to the various integrated circuits. In addition to the above-described skew associated with the delivery of the clock signal to integrated circuits within the system, there is also a skew associated with a clock delivery scheme within each integrated circuit.
As is known in the art, the skew associated with delivering the clock to various integrated circuits located at different distances from the central clock is easily minimized by providing conductors of equal lengths between the central clock and the various integrated circuits through use of additional wiring or delay elements provided in the conductors. However, this strategy of using the same conductor lengths or delay components within a particular integrated circuit is not feasible due to a significant difference in operating speed of one integrated circuit as compared to another integrated circuit. In some cases, the operating speed of two integrated circuits may vary by as much as 50 percent.
One solution to addressing the varying operation speed of integrated circuits within a system is to incorporate a phase locked loop at the input of a clock signal to an integrated circuit. A phased locked loop provides a self-correcting element to the clock signal within a particular integrated circuit so that there is minimal clock variation from integrated circuit to integrated circuit within an overall system. In the form of an example, if a clock takes 3 nanoseconds to be distributed throughout the first integrated circuit once received at the input of the first integrated circuit and the clock takes 1.50 nanoseconds to be distributed throughout a second integrated circuit once received at the input of the second integrated circuit, then there is a 2:1 ratio in the propagation speed of the distributed clock signals. Therefore, there is a 1.50 nanosecond skew between the first and second integrate circuits. A phase locked loop attempts to compensate for this skew. However, depending upon the quality of electronic components used in the phase locked loop and the design of the phased locked loop, there remains a skew associated with the system since it is virtually impossible to design and implement an ideal phase locked loop.
In order to maximize the compensation of a phase locked loop, it is important to properly select a feedback point from which the phase locked loop feedback path will be generated. Thus, a feedback point for the phase locked loop feedback path should be chosen corresponding to a final clock location within an integrated circuit. However, in current designs, a clock signal, once to the integrated circuit, is propagated to up 40,000 final clock locations. Therefore, it is impractical to determine the best location for the feedback point. Rather, one of the 40,000 final clock locations is randomly chosen as the feedback point.
A critical aspect of an electronic system is that the various components of the system must be tested to ensure proper operation and interconnection. In order to perform a test procedure (test mode), the central clock of the system is halted or stopped. Known test data is then scanned into the various electronic components of the system. The clock is then restarted at the maximum operating frequency of the system for a minimal number of clock cycles. The system clock is again halted and data is scanned out of the various electronic components. The operation of the system can be analyzed by comparing the scanned out data to expected results. This process, called xe2x80x9cstop-and-scanxe2x80x9d or xe2x80x9cstop-and-stepxe2x80x9d, ensures that data is moving within the system from location to location meeting correct timing requirements.
A significant issue associated with testing the electronic device is that the clock of the device is halted or stopped. Since the feedback point of the phase locked loop feedback path is coupled to the clock, the feedback path is broken and the phase locked loop does not maintain lock during a clock halt. As is known in the art, if a phase locked loop does not maintain lock, the function of the phase locked loop is lost. One known solution which addresses the issue of a halted clock resulting in a loss of lock for a phase locked loop is to generate a copy or xe2x80x9cdummyxe2x80x9d clock. A real clock tree can be masked off near the root of the tree to cause a clock halt, but the copy clock tree is an unmasked major branch off of the root of the clock tree. Since the copy clock tree is not masked off or halted, the clock of the real clock tree can be halted while the feedback point of the phase locked loop is generated from the copy clock, thereby maintaining its feedback path and its lock. Further, masking the real clock facilitates test procedures in that the real clock can be restarted, n-stepped, and re-halt while in the test mode.
The disadvantage of utilizing a copy of the real tree branch for maintaining lock of the phase locked loop is that it is extremely difficult to match and track the real clock tree in latency over a process and operating conditions. To the degree that this mismatch and mis-track of the copy clock is inaccurate, there is a direct increase in integrated circuit clock skew between the internal clock of the integrated circuit and an external clock. This clock skew is a severe disadvantage in normal, non-test mode. In some cases, the clock slew associated with a phase locked loop utilizing a feedback point from a copy clock may be greater than having no phase locked loop compensation. Therefore, there is a need for a clocking system and method which can maintain lock of a phase locked loop feedback path in either a normal operation mode or a test mode, while minimizing the overall skew of the system.
The present invention provides a system and method capable of maintaining lock of a phase locked loop feedback path in both a normal operation mode and a test mode, and during the switching of the system from the normal operation mode to the test mode, while minimizing the overall skew of the system.
One embodiment of the present invention provides a method of maintaining lock of a phase locked loop feedback path within an integrated circuit during both normal operation mode and test mode. The method includes closing a phase locked loop feedback path of the phase locked loop with a real clock signal from a real clock tree during the normal operation mode. The real clock tree is then halted, thereby transitioning the system from a normal mode to a test mode. The phase locked loop feedback path of the phase locked loop is closed with a copy clock signal from a copy clock tree during the test mode, such that the phase locked loop maintains lock. The steps of halting the real clock and switching the feedback point from the real clock to the copy clock are performed in a single clock cycle.
The method further includes scanning known data into electronic components of the integrated circuit during the test mode. A full speed clock is provided to the electronic component of the integrated circuit for at least one clock cycle. Data within the electronic components after the at least one clock cycle are scanned out of the electronic components of the integrated circuit. The scanned data is compared to expected data and the integrated circuit is reset after the comparison procedure.
The method further comprises providing an output signal of the phase locked loop to the real clock tree and to the copy clock tree during normal enabling mode. The step of halting within real clock tree then further includes disabling a clocking gate and the real clock tree such that an output signal of the phase locked loop does not pass through the clocking gate. Further, a phase locked loop feedback input signal is selectively controlled based upon a mode of the integrated circuit, such that the phase locked loop feedback input signal is derived from the real clock signal during normal operation mode and derived from the copy clock signal during the test mode.
The present invention also includes a system for maintaining lock of a phase lock loop within an integrated circuit during a normal mode and a test mode, and during the switching between the normal operation mode and the test mode. The system includes a phase locked loop having a clock input, a feedback input, and an output. The clock input of the phase locked loop is capable of receiving a clock signal. A clocking gate has an input electrically coupled to the output of the phase locked loop. A real clock tree is electrically coupled to an output of the clocking gate. The real clock tree provides a clock signal to electrical components of the integrated circuit. A copy clock tree is also electrically coupled to the output of the phase locked loop. A multiplexor has a first input electrically coupled to the real clock tree and a second input electrically coupled to the copy clock tree. The multiplexor has an output electrically coupled to the feedback input of the phase locked loop. A controller is electrically coupled to the clocking gate for selectively controlling the output of the clocking gate and electrically coupled to the multiplexor for selectively controlling the output of the multiplexor.